Reasons to use ASICs
An ASIC is smaller than multiple interconnected standard products on a PC board. Cell phones are as small as they are because of the presence of ASICs in their design.
Power and performance
Because of their small physical size, ASIC devices use electrical power more efficiently than a large collection of standard components. In addition, the ASIC contains only the circuitry needed for the application, so an ASIC can usually deliver the same or better performance using less power.
An ASIC protects intellectual property. It is considerably more difficult for an unscrupulous competitor to reverse-engineer and knock-off a product containing an ASIC, compared to copying a PC board containing standard products.
Although an initial investment is required to develop an ASIC, this pays off in the long run. Aside from a possible performance enhancement, a product using an ASIC requires fewer electronic components and is cheaper to assemble. Fewer parts also translates into higher reliability, and the end product’s enclosure might be smaller as well. Using ASICs in a design also reduces the number of component vendors involved in producing the end product, thereby simplifying production planning and purchasing.
NRE and Production costs defined
An ASIC must first be specified and designed, and prototype ASICs are then fabricated and tested. This initial effort occurs just once, and must occur before the ASIC can be mass-produced. These costs are called “non-recurring engineering” or NRE costs.
Production wafers containing hundreds or thousands of ASIC chips are periodically ordered. These wafers are then tested, cut up into individual “dice”, and packaged as required. These repeating production costs are incurred whenever more ASICs are needed, and determine the cost of each ASIC.
NRE cost components
Wikipedia states that “The non-recurring engineering (NRE) cost of an ASIC can run into the millions of dollars.” While this is sometimes true, Sigenics has also been involved in designs which required only several thousand dollars of NRE to produce a functional prototype. In a typical project, the dominant cost is engineering labor. In this section we will explore in more detail the phases of the ASIC development and discuss what can be done to minimize NRE costs.
Please note: the dollar amounts shown below are estimates based on our experience, and should be interpreted as representative estimates only.
Specification Development – Required
The client starts with a clear idea of how his or her product will serve the needs of the customer. These customer needs dictate the operational requirements of the product, and those product requirements then dictate the specification of the ASIC which will be used in the product. The client’s product is sometimes called the “end application”. This requirement's flow-down concept is best illustrated by a simple example:
A customer wants a product which will turn off his or her car headlights automatically after a delay.
Client product requirements:
Client determines that 30 second delay will accommodate most potential customers.
ASIC shall turn off headlights in 30 seconds +/- 2 seconds.
The ASIC specification contains many other items as well, such as the operating current, voltage and temperature ranges, device pinout, required packaging, part marking etc. The ASIC specification is essentially a very complete component data sheet.
Before the design of an ASIC can begin, the required function of the ASIC must be well-defined, and the terminal characteristics of the ASIC must be explicitly stated such that if the ASIC meets the specification, then the ASIC is guaranteed to satisfy the requirements of the client’s end application.
The specification development phase ends when both Sigenics and the client have signed-off on an acceptable ASIC specification.
In our experience, the biggest cause of delays is the failure of the client to understand exactly what the ASIC must do in order to satisfy the requirements of his or her end-application.
As ASIC designers, Sigenics knows exactly what to do to make an ASIC that behaves a certain way. What we cannot know, however, is what the ASIC really needs to do in order to satisfy the client’s product requirements. During the specification development phase, the Sigenics engineering team must work very closely with the client’s engineering team. Each team will bring design issues to the table that the other team cannot know about. The effort spent during this phase contributes greatly to the value of the ASIC, for it is here that the client’s knowledge of the customer’s need merges with Sigenics' ASIC design knowledge to produce a new-to-the-world ASIC.
Some of our clients have come to us with a nearly perfect ASIC specification, which can be signed off in a week. Others have taken nearly six months to arrive at an acceptable specification. In these longer cases, the client and/or Sigenics needed to do some testing of actual circuitry in the end application to determine exactly what would be required of the ASIC to function properly. In all cases, however, a comprehensive, signed-off ASIC specification is absolutely necessary to ensure that the client’s ASIC performance expectations are met.
Specification Development: $1k – $50k
Acceptance Test Plan (“ATP”) Development – Required
Hand-in-hand with the Specification, an ATP is necessary to show exactly how prototype ASICs will be tested with hardware to show that they meet the specification. Sigenics will work with the client to develop and sign off an ATP. If the prototype ASIC devices pass the ATP, the ASIC development is deemed successful and the ASICs will satisfy the client's stated need.
The ATP is also important because during the ASIC design phase, Sigenics engineers simulate the ASIC design against the ATP to insure the prototypes will pass the ATP. With a good starting Specification, the ATP becomes just a matter of translating the Specification into a set of tests realizable in the simulation environment and on real test equipment.
ATP Development: $1k – $10k
Schematic Design – Required
With the Specification and ATP in hand, Sigenics engineers perform the following steps which result in a schematic design of the ASIC. As stated in the last section, the simulation of this design must pass the ATP.
- Process selection – a semiconductor foundry will fabricate the ASIC. Many different foundries are available, and each of these foundries has multiple fabrication (“fab”) processes available. A particular fab process is selected based on the ASIC requirements such as size, cost, operating voltages and currents, required precision and any other special requirements like tolerance to radiation or high temperature operation.
- System architecture – alternate methods of executing the function are evaluated, and an architecture review is usually held with the client so we can explain our intended approach. An architecture decision example : implement a multiplier function using analog components rather than using a digital look-up-table. The client review allows us to identify any shortcomings early in the design process.
- Design of functional blocks – existing Sigenics IP components, like logic families, amplifiers or voltage references may be used as-is or with some modification. Other special modules must be built “from scratch” using individual transistors, capacitors, resistors, etc. Each functional block is simulated to ensure it performs its intended function.
- System top-level schematic assembly – the entire ASIC schematic is assembled using the functional blocks.
- Simulations to ATP – the entire ASIC (where practical) is simulated to ensure it meets every item in the ATP. This simulation is performed over all expected fab process variations (fast and slow NFETs and PFETs, highest and lowest resistor variation, etc.) and over the power supply and temperature ranges specified for the ASIC. If any ATP item fails the simulations, the schematic is altered to make the ASIC pass, and the design is resimulated in its entirety.
- Yield estimation – using fab-supplied bounds for lithographic errors, a projection of device yield is made to ensure that the design is manufacturable within the constraints of the program.
- Design review – a review is held with the client demonstrating how simulations show the ASIC is expected to meet all aspects of the ATP over power supply, temperature and fab process variation.
Due to the wide range of program complexity and ASIC requirements, the scope of the Schematic Design effort can vary dramatically.
There is the risk element to consider, too. The more engineering time we spend in design and simulation, the more likely it is that the first prototypes will produce an acceptable ASIC. Engineering time is expensive, however, and it may be more cost effective to plan for a second prototype run rather than spend the additional engineering time up front to lower the risk of the first prototype run. On some fab processes, prototype wafer runs can be had for as little as $20k.
On the other hand, prototype runs on more exotic processes, like those with a small feature size or radiation hardened capability, can cost over $200k. In these cases, it is worth the extra engineering effort to run more simulations upfront to further increase the likelihood of first-spin success.
Schematic Design: $5k – $250k
ASIC Physical Layout – Required
The ASIC schematic is laid out to produce a database of geometric objects on the multiple mask layers used in the selected fab process. This is done at both the lowest transistor-level, and often at higher levels, such as logic gates. After the layout is complete, a Layout Versus Schematic (“LVS”) and fab Design Rule Check (“DRC”) is performed to make sure the schematic was laid out without errors, and that all geometry in the layout conforms to the layout rules specified by the semiconductor foundry. After the physical layout is complete, “parasitics” are “extracted” and the design is resimulated.
A parasitic element is an undesired electrical component in the circuit that is an artifact of the fabrication process and physical layout, and parasitic elements are not included in the original circuit schematic. For example, a wire on the schematic is a zero-resistance connection between two points. In a real ASIC, the wires are made out of aluminum, and the resistance of a given wire depends on its composition, thickness, width and length. Since this parasitic resistor was not in the original circuit schematic, the first circuit simulations would not show how this parasitic resistance might affect the circuit operation. After layout is complete, we “extract” the value of this parasitic resistance by looking at the physical layout of that wire, then modify the original circuit schematic to include this resistance. There are also parasitic capacitances, and even parasitic transistors whose properties depend on the layout. After parasitics have been extracted and included in the circuit schematic, we resimulate the circuit with parasitics to show that the ASIC still meets the ATP performance criteria.
A layout review is held with the client before submission of the layout to the fab. During this review, the layout is explained, and the ASIC pinout, dimensions and any company logos appearing on the ASIC are verified.
ASIC Physical Layout: $2k – $150k
Prototype Tapeout – Required
The ASIC layout database is sent to the foundry for fabrication. This is called “tapeout”. Six to twelve weeks later, Sigenics receives typically 3-12 wafers containing the prototype ASIC design. These wafers are cut into die form and assembled into packages to be tested against the ATP. All items in the ATP are evaluated, and any deficiencies or “bugs” are noted. If no bugs are discovered the design moves directly into the production phase. If bugs are discovered, they may be addressed by a Specification and ATP change, or the design is modified to correct the discrepancy and a second-spin Prototype tapeout is executed after design and layout changes. Any required second-spin schematic design and layout effort is usually substantially smaller than what is required for the first-spin. Often, bugs may be corrected by changing only a single mask layer, and the second-spin prototype fab cost and lead time can be significantly less than the first.
Cost for the prototype fab run is dependent on the foundry and fab process chosen. One of our more popular processes costs about $20k for 6 wafers. One way to keep the cost of prototypes low is to share a prototype run. Since Sigenics does multiple designs in a given year, we can often put ASICs from several different clients on the same prototype fabrication run using what is called a “pizza mask”. The cost of that prototype run is then shared between multiple projects, with each client paying for only his or her fraction of the run. After dicing, all the different ASICs are separated, so confidentiality is preserved.
Prototype Fab: $20k – $250k (less if shared)
Purchase of Production Mask Set – Required for Large ASIC Volumes
Production Mask Set: $20k – $200k
The prototype mask set can be used only once, and can produce 6-12 wafers. If more ASICs are needed, a production mask set must be purchased. This mask set can be used indefinitely to produce wafers in lots of 25. After an acceptable prototype has been fabricated, the same layout database is used to make the production mask set. The cost of this mask set depends on the fab process used.
Production Test Development – Required if Testing is Required
A probe card is designed, and test equipment is assembled to allow the die on the wafer to be tested on an automatic wafer prober according to a subset of the ATP called the production test plan. A test program is written to implement this production test plan.
The result of wafer probing is a tested wafer and an electronic die map which shows which die on the wafer have passed the test.
Production Test Development: $8k – $80k
Production cost components
After all of the above NRE tasks are complete, all that remains is to “turn the crank” and produce production ASICs. The primary production cost components are shown in the list below. The three main factors determining the per-die cost of an ASIC are the die area, test time and device packaging. These costs are also volume-dependent.
Wafer cost: $1,500 – $20k per wafer (depends on fab process used)
Test time: $0.05 – $3.00 per die (depends on the length of the test required for each die)
Wafer dicing: $800-$2k per wafer (depends on wafer size and die/wafer)
Picking and visual inspection: $0.05-$0.75 per die (depends on level of inspection required)
Packaging: $0.30-$5.00 (depends on package type and volume)
Shipping and documentation (depends on level of traceability required)
Financial Concerns and Real Examples
Along with the different technical aspects of each ASIC design, the financial environment of every ASIC program is different. On some programs, funding must be spent according to a strict timetable. Sometimes a client may wish to amortize the NRE costs over a production device order. Sigenics is also flexible enough to participate as a financial partner in some ASIC programs.
Shown below are some representative cost examples of ASIC projects we’ve done for our clients.
a). A military-grade analog bus driver/receiver
NRE: $225k $7.50 in 100k/yr quantities
b). A wireless industrial sensor used to monitor the liquid level in petroleum storage tanks
NRE: $60k Price/device: $25 in 1k/yr quantities
c). A military-grade IR LED driver
NRE: $60k Price/device: $1.50 in 50k/yr quantities (bare die)
d). A multichannel bioelectric amplifier for a research program
NRE: $50k Price/device: $0 (evaluation units supplied from shared prototype run)
e). A radiation-hardened space-grade analog power driver and sensing device
NRE: $850k Price/device: $86 in 10k/yr quantities